Invention Grant
US09252213B2 Integrated circuits with a buried N layer and methods for producing such integrated circuits
有权
具有掩埋N层的集成电路和用于制造这种集成电路的方法
- Patent Title: Integrated circuits with a buried N layer and methods for producing such integrated circuits
- Patent Title (中): 具有掩埋N层的集成电路和用于制造这种集成电路的方法
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Application No.: US14134731Application Date: 2013-12-19
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Publication No.: US09252213B2Publication Date: 2016-02-02
- Inventor: Zhang Guowei , Purakh Raj Verma
- Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Current Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Current Assignee Address: SG Singapore
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/06 ; H01L21/324 ; H01L21/762 ; H01L21/02 ; H01L21/265 ; H01L21/3205
Abstract:
Integrated circuits with a buried N layer and methods for fabricating such integrated circuits are provided. The method includes forming a buried N layer overlying a substrate, and forming a monocrystalline layer overlying the buried N layer. After forming the monocrystalline layer, a well tap trench is formed, where the well tap trench penetrates the electronics area and the buried N layer and extends into the substrate. A well tap is formed in the well tap trench.
Public/Granted literature
- US20150179734A1 INTEGRATED CIRCUITS WITH A BURIED N LAYER AND METHODS FOR PRODUCING SUCH INTEGRATED CIRCUITS Public/Granted day:2015-06-25
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