Invention Grant
US09252157B2 Method to form group III-V and Si/Ge FINFET on insulator and integrated circuit fabricated using the method
有权
使用该方法制造的III-V族和Si / Ge型FINFET绝缘子和集成电路的方法
- Patent Title: Method to form group III-V and Si/Ge FINFET on insulator and integrated circuit fabricated using the method
- Patent Title (中): 使用该方法制造的III-V族和Si / Ge型FINFET绝缘子和集成电路的方法
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Application No.: US14711019Application Date: 2015-05-13
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Publication No.: US09252157B2Publication Date: 2016-02-02
- Inventor: Lukas Czornomaz , Jean Fompeyrine , Effendi Leobandung
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Harrington & Smith
- Agent Louis J. Percello
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L27/092 ; H01L21/84 ; H01L29/161 ; H01L29/20 ; H01L21/02 ; H01L29/78 ; H01L21/8238

Abstract:
A method includes providing a structure having a substrate, a first electrically insulating layer overlying the substrate, a first semiconductor layer comprised of a first semiconductor material overlying the first electrically insulating layer, a second electrically insulating layer overlying the first semiconductor layer in a first portion of the structure and a second semiconductor layer comprised of a second, different semiconductor material overlying the second electrically insulating layer in the first portion. The method further includes growing additional first semiconductor material on the first semiconductor layer in a second portion of the structure to form a regrown semiconductor layer; forming fins; forming gate structures orthogonal to the fins and removing at least a portion of the first semiconductor layer in the first portion of the structure to form a void and filling the void with insulating material. Structures formed by the method are also disclosed.
Public/Granted literature
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