Invention Grant
US09252148B2 Methods and apparatuses with vertical strings of memory cells and support circuitry
有权
具有垂直的存储单元串和支持电路的方法和装置
- Patent Title: Methods and apparatuses with vertical strings of memory cells and support circuitry
- Patent Title (中): 具有垂直的存储单元串和支持电路的方法和装置
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Application No.: US14161170Application Date: 2014-01-22
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Publication No.: US09252148B2Publication Date: 2016-02-02
- Inventor: Takehiro Hasegawa , Koji Sakui
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G11C16/04
- IPC: G11C16/04 ; H01L27/115 ; H01L29/78 ; H01L29/66 ; G11C5/14
Abstract:
Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. Support circuitry is formed on the backside of the substrate and coupled to the strings of memory cells through vertical interconnects in the substrate. The vertical interconnects can be transistors, such as surround substrate transistors and/or surround gate transistors.
Public/Granted literature
- US20150206587A1 METHODS AND APPARATUSES WITH VERTICAL STRINGS OF MEMORY CELLS AND SUPPORT CIRCUITRY Public/Granted day:2015-07-23
Information query
