Invention Grant
- Patent Title: Stacked semiconductor package and method for manufacturing the same
- Patent Title (中): 堆叠半导体封装及其制造方法
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Application No.: US14536002Application Date: 2014-11-07
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Publication No.: US09252139B2Publication Date: 2016-02-02
- Inventor: Hyeong Seok Choi
- Applicant: SK hynix Inc.
- Applicant Address: KR Gyeonggi-do
- Assignee: SK Hynix Inc.
- Current Assignee: SK Hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: William Park & Associates Ltd.
- Priority: KR10-2012-0047065 20120503
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L25/00 ; H01L23/498 ; H01L21/78 ; H01L23/31 ; H01L25/065 ; H01L25/10 ; H01L21/768 ; H01L21/56 ; H01L23/00

Abstract:
A stacked semiconductor package includes a first semiconductor chip having a first surface and a second surface which faces away from the first surface and including first bonding pads which are formed on the first surface and first through electrodes which pass through the first surface and the second surface; a second semiconductor chip stacked over the second surface of the first semiconductor chip, and including second bonding pads which are formed on a third surface facing the first semiconductor chip and second through electrodes which pass through the third surface and a fourth surface facing away from the third surface and are electrically connected with the first through electrodes; and a molding part formed to substantially cover the stacked first and second semiconductor chips and having openings which expose one end of the first through electrodes disposed on the first surface of the first semiconductor chip.
Public/Granted literature
- US20150064843A1 STACKED SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2015-03-05
Information query
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