Invention Grant
- Patent Title: Interconnect arrangement with stress-reducing structure and method of fabricating the same
- Patent Title (中): 具有应力降低结构的互连装置及其制造方法
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Application No.: US14162158Application Date: 2014-01-23
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Publication No.: US09252047B2Publication Date: 2016-02-02
- Inventor: Yi-Ruei Lin , Yen-Ming Peng , Han-Wei Yang , Chen-Chung Lai
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
- Current Assignee Address: TW Hsin-Chu
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/48 ; H01L23/31 ; H01L23/00
Abstract:
Embodiments of a semiconductor device structure and a method of fabricating the same are provided. The semiconductor device structure includes a substrate and a first layer formed over the substrate. The semiconductor device structure further includes a stress-reducing structure formed in the first layer, and a portion of the first layer is surrounded by the stress-reducing structure. The semiconductor device structure further includes a conductive feature formed in the portion of the first layer surrounded by the stress-reducing structure.
Public/Granted literature
- US20150206845A1 INTERCONNECT ARRANGEMENT WITH STRESS-REDUCING STRUCTURE AND METHOD OF FABRICATING THE SAME Public/Granted day:2015-07-23
Information query
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