Invention Grant
US09251915B2 Seamless fail analysis with memory efficient storage of fail lists 有权
无效故障分析与故障列表的存储器高效存储

Seamless fail analysis with memory efficient storage of fail lists
Abstract:
A method for testing memory devices under test (DUTs) using automated test equipment (ATE) is presented. The method comprises retrieving a portion of raw test data from a memory device under test (DUT). It also comprises comparing the portion of raw test data with expected test data to determine failure information, wherein the failure information comprises information regarding failing bits generated by the memory DUT. Next, the method comprises utilizing paging to transfer data comprising the failure information to a filtering module and filtering out the failure information from transferred data using the filtering module. Further, it comprises updating a fail list using the failure information, wherein the fail list comprises address information for respective failing bits within the memory DUT. Finally, it comprises repeating all the prior steps for the next block of raw test data.
Public/Granted literature
Information query
Patent Agency Ranking
0/0