Invention Grant
- Patent Title: Interconnect structure and forming method thereof
- Patent Title (中): 互连结构及其形成方法
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Application No.: US14108860Application Date: 2013-12-17
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Publication No.: US09230855B2Publication Date: 2016-01-05
- Inventor: Ernest Li
- Applicant: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
- Applicant Address: CN Pudong, Shanghai
- Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
- Current Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
- Current Assignee Address: CN Pudong, Shanghai
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: CN201210556457 20121219
- Main IPC: H01L21/4763
- IPC: H01L21/4763 ; H01L21/768 ; H01L23/522 ; H01L23/532
Abstract:
An interconnect structure and a forming method thereof are provided. The method includes: providing a semiconductor substrate which has semiconductor devices formed therein; forming a conductive layer on the semiconductor substrate; forming a mask layer on the conductive layer; forming a groove in the mask layer and the conductive layer, the groove having a depth-to-width ratio greater than 0.8; and depositing an intermetallic dielectric layer to cover the mask layer and fill the groove, wherein an air gap is formed in a portion of the intermetallic dielectric layer in the groove. The mask layer is formed on the conductive layer, so that the depth-to-width ratio of the groove between adjacent interconnects is increased. Besides, the air gap with a relatively large size is formed between two adjacent interconnects. Therefore, a dielectric constant and parasitic capacitance between adjacent interconnects are reduced evidently, and the performance of the semiconductor devices is improved.
Public/Granted literature
- US20140167271A1 INTERCONNECT STRUCTURE AND FORMING METHOD THEREOF Public/Granted day:2014-06-19
Information query
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