Invention Grant
- Patent Title: Semiconductor devices including spacers on sidewalls of conductive lines and methods of manufacturing the same
- Patent Title (中): 包括导线侧壁上的间隔物的半导体器件及其制造方法
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Application No.: US14514207Application Date: 2014-10-14
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Publication No.: US09099302B2Publication Date: 2015-08-04
- Inventor: Jong Pil Lee
- Applicant: SK hynix Inc.
- Applicant Address: KR Icheon-si
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR Icheon-si
- Agency: Kilpatrick Townsend & Stockton LLP
- Priority: KR10-2012-0083537 20120730
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L23/538 ; H01L21/48 ; H01L27/108 ; H01L21/768

Abstract:
Semiconductor devices are provided that include spacers on sidewalls of conductive lines, as well as methods for manufacturing the same. A method for manufacturing a semiconductor device includes forming bit lines on a semiconductor substrate. Triple-layered bit line spacers are formed on respective sidewalls of the bit lines. An interlayer insulation layer is formed on the bit lines and the triple-layered bit line spacers. Storage node contact plugs that penetrate the interlayer insulation layer are formed between the bit lines. Portions of the triple-layered bit line spacers are etched to form recessed regions. An insulation layer is formed on the substrate including the recessed regions. Storage node electrodes electrically connected to the storage node contact plugs are formed.
Public/Granted literature
Information query
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