An apparatus includes a memory module with a plurality of memory blocks and an address decoder module that decodes one or more address lines of the plurality of memory blocks. An address output of the address decoder module corresponds to each memory block. A BWE module includes a block write enable (“BWE”) signal corresponding to each memory block. Each BWE signal has a block write enable state and a block write disable state. In response to receiving a block write enable control (“BWEC”) signal in a normal use mode, a MUX module passes a corresponding address output of the address decoder module to a write enable input of each memory block. In response to receiving the BWEC signal in a state trace mode, the MUX module passes a corresponding BWE signal to the write enable input of each memory block.