A phase estimator comprising a first input terminal configured to receive a first analog input signal; a second input terminal configured to receive a second analog input signal, wherein the second analog input signal is 90° out of phase with the first analog input signal. The phase estimator is configured to provide a digital word representative of the phase of the first analog input signal and the second analog input signal. The phase estimator comprises a register configured to store N bits as a digital word a first reference signal generator, a second reference signal generator and a comparator.