Invention Grant
US09076837B2 Lateral insulated gate bipolar transistor structure with low parasitic BJT gain and stable threshold voltage
有权
具有低寄生BJT增益和稳定阈值电压的横向绝缘栅双极晶体管结构
- Patent Title: Lateral insulated gate bipolar transistor structure with low parasitic BJT gain and stable threshold voltage
- Patent Title (中): 具有低寄生BJT增益和稳定阈值电压的横向绝缘栅双极晶体管结构
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Application No.: US13543662Application Date: 2012-07-06
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Publication No.: US09076837B2Publication Date: 2015-07-07
- Inventor: Long-Shih Lin , Kun-Ming Huang , Ming-Yi Lin
- Applicant: Long-Shih Lin , Kun-Ming Huang , Ming-Yi Lin
- Applicant Address: TW
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW
- Agency: Lowe Hauptman & Ham, LLP
- Main IPC: H01L29/49
- IPC: H01L29/49 ; H01L29/739 ; H01L29/66 ; H01L29/06 ; H01L29/08 ; H01L29/10 ; H01L29/423
Abstract:
A metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly a lateral insulated gate bipolar junction transistor (LIGBT), and a method of making it are provided in this disclosure. The device includes a silicon-on-insulator (SOI) substrate having a drift region, two oppositely doped well regions in the drift region, two insulating structures over and embedded in the drift region and second well region, a gate structure, and a source region in the second well region over a third well region embedded in the second well region. The third well region is disposed between the gate structure and the second insulating structure.
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