Invention Grant
US09076824B2 Memory arrays with a memory cell adjacent to a smaller size of a pillar having a greater channel length than a memory cell adjacent to a larger size of the pillar and methods
有权
具有与较小尺寸的柱相邻的存储器阵列的存储器阵列具有比与较大尺寸的柱相邻的存储器单元的通道长度更大的通道长度
- Patent Title: Memory arrays with a memory cell adjacent to a smaller size of a pillar having a greater channel length than a memory cell adjacent to a larger size of the pillar and methods
- Patent Title (中): 具有与较小尺寸的柱相邻的存储器阵列的存储器阵列具有比与较大尺寸的柱相邻的存储器单元的通道长度更大的通道长度
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Application No.: US13667649Application Date: 2012-11-02
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Publication No.: US09076824B2Publication Date: 2015-07-07
- Inventor: Koji Sakui , Peter Feeley
- Applicant: MICRON TECHNOLOGY, INC
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dicke, Billig & Czaja, PLLC
- Main IPC: G11C16/04
- IPC: G11C16/04 ; H01L29/66 ; H01L29/788 ; H01L29/792 ; H01L27/115
Abstract:
The disclosure is related to memory arrays and methods. One such memory array has a substantially vertical pillar. A memory cell adjacent to the pillar where the pillar has a first size has a greater channel length than a memory cell adjacent to the pillar where the pillar has a second size larger than the first size.
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