A semiconductor memory device comprises a first-supplied-voltage-supplying pad, a second-supplied-voltage-supplying pad, a data input/output pad, a memory body, a buffer circuit and an impedance-controlling circuit. A first supplied voltage is supplied to the memory body. A second supplied voltage is supplied to the buffer circuit. The impedance-controlling circuit controls an impedance of the buffer circuit on a side connected to the data input/output pad. The semiconductor memory device comprises a voltage-generating circuit generating a first inner voltage. The impedance-controlling circuit comprises a first P-channel transistor. A source terminal of the first P-channel transistor is connected to the first-supplied-voltage-supplying pad, and the first inner voltage generated from the voltage-generating circuit is selectively supplied to a gate terminal of the first P-channel transistor.