To be provided is a control circuit including a horizontal synchronization clock counting unit that counts the number of clock cycles of a horizontal synchronization clock signal for instructing a timing of starting scanning pixels in a horizontal direction of a pixel group arranged in a two-dimensional lattice shape, so as to be used as a horizontal synchronization clock count value, a high frequency clock counting unit that counts the number of clock cycles of a high frequency clock signal with a higher frequency than the horizontal synchronization clock signal, so as to be used as a high frequency clock count value, and a timing determination unit that determines timings of starting and ending exposure for the pixels on the basis of the horizontal synchronization clock count value and the high frequency clock count value.