Invention Grant
- Patent Title: Chip edge sealing
- Patent Title (中): 芯片边缘密封
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Application No.: US14032437Application Date: 2013-09-20
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Publication No.: US09054150B2Publication Date: 2015-06-09
- Inventor: Markus Zundel , Gabriela Brase , Peter Nelle , Guenther Schindler
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Shumaker & Sieffert, P.A.
- Priority: DE102012018611 20120920
- Main IPC: H01L29/739
- IPC: H01L29/739 ; H01L29/78 ; H01L23/31 ; H01L29/40 ; H01L29/06
Abstract:
The invention relates to a semiconductor component comprising a semiconductor body, an insulation on the semiconductor body and a cell array arranged at least partly within the semiconductor body. The cell array has at least one p-n junction and at least one contact connection. The insulation is bounded in lateral direction of the semiconductor body by a circumferential diffusion barrier.
Public/Granted literature
- US20140077262A1 CHIP EDGE SEALING Public/Granted day:2014-03-20
Information query
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