Invention Grant
- Patent Title: Integrated circuit having staggered bond pads and I/O cells
- Patent Title (中): 集成电路具有交错的接合焊盘和I / O单元
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Application No.: US13716479Application Date: 2012-12-17
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Publication No.: US09054084B2Publication Date: 2015-06-09
- Inventor: Rajendra D Pendse
- Applicant: Rajendra D Pendse
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Ltd.
- Current Assignee: STATS ChipPAC Ltd.
- Current Assignee Address: SG Singapore
- Agency: Ishimaru & Associates LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/488 ; H01L23/00 ; H01L27/118

Abstract:
Staggered bond ads and I/O cells are arranged on an integrated circuit. The integrated circuit includes at least a first I/O cell having a first bond pad and first opposing set of recesses, a second I/O cell having a second bond sad and second opposing set of recesses, and a third I/O cell having a third bond sad and third opposing set of recesses. Each set of opposing recesses can be arranged in a staggered formation to receive adjacent bond pads, which can also be configured in a staggered formation.
Public/Granted literature
- US20130127061A1 INTEGRATED CIRCUIT PACKAGE SYSTEM Public/Granted day:2013-05-23
Information query
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