Invention Grant
- Patent Title: Non-volatile memory circuit
- Patent Title (中): 非易失性存储器电路
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Application No.: US14097298Application Date: 2013-12-05
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Publication No.: US09053798B2Publication Date: 2015-06-09
- Inventor: Ayako Kawakami , Kazuhiro Tsumura
- Applicant: SEIKO INSTRUMENTS INC.
- Applicant Address: JP
- Assignee: SEIKO INSTRUMENTS INC.
- Current Assignee: SEIKO INSTRUMENTS INC.
- Current Assignee Address: JP
- Agency: Adams & Wilks
- Priority: JP2012-269761 20121210
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C16/12 ; G11C16/04

Abstract:
A non-volatile memory circuit is formed of a P-channel MOS transistor and includes a P-channel non-volatile memory element having a floating gate and a control gate capacitively coupled together. A resistor divider has a first resistor and a second resistor for dividing a voltage difference between a power supply voltage and a ground voltage. A divided voltage output of the resistor divider is connected to the control gate. First and second switches are connected in parallel to the respective first and second resistors. The first and second switches are controlled so that a voltage of the control gate is set to a voltage of the divided voltage output which maximizes an electric field between a pinch-off point and a drain point of the P-channel MOS transistor in a writing mode.
Public/Granted literature
- US20140160860A1 NON-VOLATILE MEMORY CIRCUIT Public/Granted day:2014-06-12
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