Invention Grant
US09053762B2 Pipeline-controlled semiconductor memory device with reduced power consumption and memory access time
有权
管道控制的半导体存储器件具有降低的功耗和存储器访问时间
- Patent Title: Pipeline-controlled semiconductor memory device with reduced power consumption and memory access time
- Patent Title (中): 管道控制的半导体存储器件具有降低的功耗和存储器访问时间
-
Application No.: US13468626Application Date: 2012-05-10
-
Publication No.: US09053762B2Publication Date: 2015-06-09
- Inventor: Atsunori Hirobe
- Applicant: Atsunori Hirobe
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Foley & Lardner LLP
- Priority: JP2011-105119 20110510
- Main IPC: G11C7/10
- IPC: G11C7/10 ; G11C11/4076
Abstract:
A semiconductor device includes a memory cell array including a plurality of memory array basic units. A first bus for transfer of address/control signals, includes a first buffer circuit operating as a pipeline register. A second bus for bidirectional transfer of write/read data, includes a second buffer circuit operating as a pipeline register. A first control circuit sequentially sends the address/control signals on the first bus, and a second control circuit sequentially sends/receives write/read data on the second bus.
Public/Granted literature
- US20120287729A1 SEMICONDUCTOR DEVICE Public/Granted day:2012-11-15
Information query
