Method and apparatus of hardware acceleration of EDA tools for a programmable logic device

Invention Grant

US09053272B2 Method and apparatus of hardware acceleration of EDA tools for a programmable logic device 有权

Title translation: 用于可编程逻辑器件的EDA工具的硬件加速方法和装置

Patent Title: Method and apparatus of hardware acceleration of EDA tools for a programmable logic device
Patent Title (中): 用于可编程逻辑器件的EDA工具的硬件加速方法和装置
Application No.: US13420002

Application Date: 2012-03-14
Publication No.: US09053272B2

Publication Date: 2015-06-09
Inventor: Edward F. Panofsky , Richard A. Karp
Applicant: Edward F. Panofsky , Richard A. Karp
Applicant Address: US CA Mountain View
Assignee: TicTran Corp.
Current Assignee: TicTran Corp.
Current Assignee Address: US CA Mountain View
Agency: Haynes Beffel & Wolfeld LLP
Agent Kenta Suzue
Main IPC: G06F17/50
IPC: G06F17/50

Abstract:

Disclosed is a hardware accelerator for development engineering processes for a programmable logic device, such as for an FPGA.

Abstract(Chinese):

公开了用于可编程逻辑器件（例如FPGA）的开发工程过程的硬件加速器。

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