Invention Grant
US09053265B2 Generating test benches for pre-silicon validation of retimed complex IC designs against a reference design
有权
根据参考设计生成重新定位的复杂IC设计的硅前验证测试台
- Patent Title: Generating test benches for pre-silicon validation of retimed complex IC designs against a reference design
- Patent Title (中): 根据参考设计生成重新定位的复杂IC设计的硅前验证测试台
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Application No.: US13648734Application Date: 2012-10-10
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Publication No.: US09053265B2Publication Date: 2015-06-09
- Inventor: Mark H. Nodine
- Applicant: Apple Inc.
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- Agent Anthony M. Petro
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
This invention (900) described a method that generates and uses a test bench for verifying an electrical design module in a semiconductor manufacturing against an electrical reference model containing a sub-circuit that matches the electrical design module. The invention includes providing (902) a description of an electrical design module that includes a plurality of ports. In addition, the invention includes providing (904) a description of an electrical reference model. The invention further includes providing and or creating (92) one or more implicit defines for the reference modules that appear in hierarchy of the electrical reference model. And, the invention includes providing (906) a description file that includes one or more instance definitions. The invention parses (91) the hierarchy of the electrical design model and then processes (96) the description file. The invention then writes (97) the test bench.
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