An integrated circuit (IC) generates clock delay control signals based on its operational voltage level. The clock delay control signals are routed to corresponding clock gating logic that controls the synchronous capturing of the outputs of corresponding signal paths. The clock gating logic delays the clock signal used by the corresponding flip-flop in response to an assertion of the corresponding received clock delay control. Thus, the clock signal used to capture the outputs of certain signal paths may be delayed under certain voltage conditions. This selective clock path delay for different signal paths enables the IC to use a higher clock frequency, or more reliably latch the path outputs at a certain clock frequency, even though different signal paths may exhibit different relative path delays under different operating voltage conditions.