Invention Grant
- Patent Title: Processes of making pad-less interconnect for electrical coreless substrate
- Patent Title (中): 制造无电芯基板的无焊接互连的工艺
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Application No.: US12215018Application Date: 2008-06-24
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Publication No.: US09049807B2Publication Date: 2015-06-02
- Inventor: Javier Soto , Charan Gurumurthy , Robert Nickerson , Debendra Mallik
- Applicant: Javier Soto , Charan Gurumurthy , Robert Nickerson , Debendra Mallik
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Winkle, PLLC
- Main IPC: H05K3/36
- IPC: H05K3/36 ; H05K3/40 ; H01L21/48 ; H01L23/498 ; H05K3/46 ; H01L23/31 ; H05K1/11 ; H05K3/00 ; H05K3/20 ; H05K3/24 ; H05K3/28 ; H05K3/34
Abstract:
A microelectronic device includes a laminated mounting substrate including a die side and a land side with a surface finish layer disposed in a recess on the mounting substrate die side. An electrically conductive first plug is in contact with the surface finish layer and an electrically conductive subsequent plug is disposed on the mounting substrate land side and it is electrically coupled to the electrically conductive first plug and disposed directly below the electrically conductive first plug.
Public/Granted literature
- US20090314519A1 Direct layer laser lamination for electrical bump substrates, and processes of making same Public/Granted day:2009-12-24
Information query
