Invention Grant
US09048874B2 Min-sum based hybrid non-binary low density parity check decoder
有权
基于最小和混合非二进制低密度奇偶校验解码器
- Patent Title: Min-sum based hybrid non-binary low density parity check decoder
- Patent Title (中): 基于最小和混合非二进制低密度奇偶校验解码器
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Application No.: US13886103Application Date: 2013-05-02
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Publication No.: US09048874B2Publication Date: 2015-06-02
- Inventor: Chung-Li Wang , Zongwang Li , Shu Li , Fan Zhang , Shaohua Yang
- Applicant: LSI Corporation
- Applicant Address: US CA San Jose
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA San Jose
- Agency: Hamilton DeSanctis & Cha
- Main IPC: H03M13/00
- IPC: H03M13/00 ; H03M13/13 ; H03M13/11

Abstract:
An apparatus for decoding data includes a variable node processor, a check node processor, and a field transformation circuit. The variable node processor is operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages and to calculate checksums based on variable node to check node messages. The variable node processor and the check node processor comprise different Galois fields. The field transformation circuit is operable to transform the variable node to check node messages from a first of the different Galois fields to a second of the Galois fields.
Public/Granted literature
- US20140281787A1 Min-Sum Based Hybrid Non-Binary Low Density Parity Check Decoder Public/Granted day:2014-09-18
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