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US09048874B2 Min-sum based hybrid non-binary low density parity check decoder 有权
基于最小和混合非二进制低密度奇偶校验解码器

Min-sum based hybrid non-binary low density parity check decoder
Abstract:
An apparatus for decoding data includes a variable node processor, a check node processor, and a field transformation circuit. The variable node processor is operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages and to calculate checksums based on variable node to check node messages. The variable node processor and the check node processor comprise different Galois fields. The field transformation circuit is operable to transform the variable node to check node messages from a first of the different Galois fields to a second of the Galois fields.
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