A DC surge protection circuit for protecting hardware from surges. During operation when no surge condition is present, the circuit passes signals from an input to an output through an inductance. When a surge is present, the circuit conducts a portion of the surge through at least one diode and diverts the surge to a ground node. A gas tube begins to conduct a portion of the surge above a first voltage level after the at least one diode first begins to conduct. A first MOV begins to conduct a portion of the surge above a second voltage level after the gas tube begins to conduct. The circuit may include a status portion. The circuit may be within an enclosure for plug-in to a motherboard or within an enclosure of an in-line connector for connection with a cable. The circuit may be configured to attach directly to a frame.