By configuring an ESD protection element of an NPN transistor (101), it is possible to reduce the area of the ESD protection element and reduce the voltage in a region in which the current increases sharply, and thus possible to increase ESD tolerance. Also, it is possible to provide a highly reliable semiconductor device wherein it is possible to flatten and smooth the surface of an upper layer pad electrode (16) by dividing a pad electrode (8) into a two-layer structure sandwiching an interlayer insulating film (15), and possible to increase the junction strength of a bonding wire, and suppress damage to underlying silicon layers when bonding.