Invention Grant
- Patent Title: Off-chip vias in stacked chips
- Patent Title (中): 堆叠芯片中的片外通孔
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Application No.: US13914896Application Date: 2013-06-11
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Publication No.: US09048234B2Publication Date: 2015-06-02
- Inventor: Belgacem Haba , Ilyas Mohammed , Vage Oganesian , David Ovrutsky , Laura Wills Mirkarimi
- Applicant: Tessera, Inc.
- Applicant Address: US CA San Jose
- Assignee: Tessera, Inc.
- Current Assignee: Tessera, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: H01L25/00
- IPC: H01L25/00 ; H01L21/683 ; H01L21/78 ; H01L23/538 ; H01L23/00 ; H01L25/065

Abstract:
A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.
Public/Granted literature
- US20130273693A1 OFF-CHIP VIAS IN STACKED CHIPS Public/Granted day:2013-10-17
Information query
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