Invention Grant
- Patent Title: Method of forming a step pattern structure
- Patent Title (中): 形成台阶图案结构的方法
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Application No.: US13910734Application Date: 2013-06-05
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Publication No.: US09048193B2Publication Date: 2015-06-02
- Inventor: Jung-Ik Oh , Dae-Hyun Jang , Seong-Soo Lee , Han-Na Cho
- Applicant: Jung-Ik Oh , Dae-Hyun Jang , Seong-Soo Lee , Han-Na Cho
- Applicant Address: KR Suwon-Si, Gyeonggi-Do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-Si, Gyeonggi-Do
- Agency: F. Chau & Associates, LLC
- Priority: KR10-2012-0093498 20120827
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/308 ; H01L21/768 ; H01L21/311 ; H01L27/115 ; H01L21/027

Abstract:
A method of forming a multi-floor step pattern structure includes forming a stacked structure having alternating insulating interlayers and sacrificial layers on a substrate. A first photoresist pattern is formed on the stacked structure. A first preliminary step pattern structure is formed by etching portions of the stacked structure using the first photoresist pattern as an etching mask. A passivation layer pattern is formed on upper surfaces of the first photoresist pattern and the first preliminary step pattern structure. A second photoresist pattern is formed by removing a side wall portion of the first photoresist pattern exposed by the passivation layer pattern. A second preliminary step pattern structure is formed by etching exposed insulating interlayers and underlying sacrificial layers using the second photoresist pattern as an etching mask. The above steps may be repeated on the second preliminary step pattern structure to form the multi-floor step pattern structure.
Public/Granted literature
- US20140057429A1 Method of Forming a Step Pattern Structure Public/Granted day:2014-02-27
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