Invention Grant
US09037938B2 Hardware architecture and implementation of low power layered multi-level LDPC decoder
有权
低功耗分层多级LDPC解码器的硬件架构与实现
- Patent Title: Hardware architecture and implementation of low power layered multi-level LDPC decoder
- Patent Title (中): 低功耗分层多级LDPC解码器的硬件架构与实现
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Application No.: US13664071Application Date: 2012-10-30
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Publication No.: US09037938B2Publication Date: 2015-05-19
- Inventor: Lei Chen , Johnson Yen , Zongwang Li , Chung-Li Wang
- Applicant: LSI Corporation
- Applicant Address: SG Singapore
- Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
- Current Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Suiter Swantz pc llo
- Main IPC: H03M13/00
- IPC: H03M13/00 ; H03M13/11
Abstract:
A layered LDPC decoder sorts and selects a subset of message entries for processing based on entry size. MIN1 and MIN2 values for each message entry in the subset are truncated, and either the truncated values or non-truncated values are combined with a symbol vector based on whether the subset of message entries includes a variable node associated with the layer being processed.
Public/Granted literature
- US20140122979A1 Hardware Architecture and Implementation of Low Power Layered Multi-Level LDPC Decoder Public/Granted day:2014-05-01
Information query
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