Invention Grant
US09037807B2 Processor arrangement on a chip including data processing, memory, and interface elements
有权
芯片上的处理器布置，包括数据处理，存储器和接口元件
- Patent Title: Processor arrangement on a chip including data processing, memory, and interface elements
- Patent Title (中): 芯片上的处理器布置，包括数据处理，存储器和接口元件
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Application No.: US12944068Application Date: 2010-11-11
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Publication No.: US09037807B2Publication Date: 2015-05-19
- Inventor: Martin Vorbach
- Applicant: Martin Vorbach
- Applicant Address: DE Munich
- Assignee: PACT XPP TECHNOLOGIES AG
- Current Assignee: PACT XPP TECHNOLOGIES AG
- Current Assignee Address: DE Munich
- Agent Edward P. Heller, III
- Priority: DE10110530 20010305; DE10111014 20010307; WOPCT/EP01/06703 20010613; DE10129237 20010620; EP01115021 20010620; DE10135210 20010724; DE10135211 20010724; WOPCT/EP01/08534 20010724; DE10139170 20010816; DE10142231 20010829; DE10142894 20010903; DE10142903 20010903; DE10142904 20010903; DE10144732 20010911; DE10144733 20010911; DE10145792 20010917; DE10145795 20010917; DE10146132 20010919; WOPCT/EP01/11299 20010930; WOPCT/EP01/11593 20011008; DE10154259 20011105; DE10154260 20011105; EP01129923 20011214; EP02001331 20020118; DE10202044 20020119; DE10202175 20020120; DE10202653 20020215; DE10206856 20020218; DE10206857 20020218; DE10207224 20020221; DE10207225 20020221; DE10207226 20020221
- Main IPC: G06F13/14
- IPC: G06F13/14 ; G06F11/20 ; G06F13/16 ; G06F12/00 ; G06F13/40 ; G06F3/06 ; G06F11/14
Abstract:
At the inputs and/or outputs, memories are assigned to a reconfigurable module to achieve decoupling of internal data processing and in particular decoupling of the reconfiguration cycles from the external data streams (to/from peripherals, memories, etc.).
Public/Granted literature
- US20110060942A1 METHODS AND DEVICES FOR TREATING AND/OR PROCESSING DATA Public/Granted day:2011-03-10
Information query
