Invention Grant
US09036747B2 Wireless communication receiver with phase noise estimation and phase noise compensation performed after channel estimation, and related wireless communication receiving method and phase noise compensation apparatus 有权
在信道估计之后进行相位噪声估计和相位噪声补偿的无线通信接收机,以及相关的无线通信接收方法和相位噪声补偿装置

  • Patent Title: Wireless communication receiver with phase noise estimation and phase noise compensation performed after channel estimation, and related wireless communication receiving method and phase noise compensation apparatus
  • Patent Title (中): 在信道估计之后进行相位噪声估计和相位噪声补偿的无线通信接收机,以及相关的无线通信接收方法和相位噪声补偿装置
  • Application No.: US13293084
    Application Date: 2011-11-09
  • Publication No.: US09036747B2
    Publication Date: 2015-05-19
  • Inventor: Chia-Hsien ChiangChing-Shyang MaaChih-Hsiu Lin
  • Applicant: Chia-Hsien ChiangChing-Shyang MaaChih-Hsiu Lin
  • Applicant Address: TW Science-Based Industrial Park, Hsin-Chu
  • Assignee: MEDIATEK INC.
  • Current Assignee: MEDIATEK INC.
  • Current Assignee Address: TW Science-Based Industrial Park, Hsin-Chu
  • Agent Winston Hsu; Scott Margo
  • Main IPC: H04B1/10
  • IPC: H04B1/10 H04L25/02 H04L27/26 H04L27/00
Wireless communication receiver with phase noise estimation and phase noise compensation performed after channel estimation, and related wireless communication receiving method and phase noise compensation apparatus
Abstract:
A wireless communication receiver includes a first signal processing block, a phase noise compensation apparatus, and a second signal processing block. The first signal processing block is arranged for generating a first processed output by processing a reception signal, wherein the first signal processing block includes a channel estimation unit arranged for performing channel estimation. The phase noise compensation apparatus is arranged for receiving the first processed output and generating a second processed output by performing phase noise compensation according to the received first processed output. The second signal processing block is arranged for receiving the second processed output and processing the received second processed output.
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