Invention Grant
- Patent Title: Circuit boards with vias exhibiting reduced via capacitance
- Patent Title (中): 具有通孔的电路板通过电容降低
-
Application No.: US13289987Application Date: 2011-11-04
-
Publication No.: US09035197B2Publication Date: 2015-05-19
- Inventor: Eric R. Ao
- Applicant: Eric R. Ao
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Sherman IP LLP
- Agent Kenneth L. Sherman; Hemavathy Perumal
- Main IPC: H05K1/11
- IPC: H05K1/11 ; H05K1/02

Abstract:
The present invention relates to circuit boards and, more specifically, circuit boards with vias (i.e. via holes) exhibiting reduced via capacitance. In one embodiment, the present invention provides a circuit board comprising a first electrically conductive trace, a second electrically conductive trace, a via hole including electrically conductive material thereon, and a coupling element that electrically connects the first trace to the second trace. The coupling element comprises a segment of the via hole that bridges the first trace and the second trace, wherein the via hole segment is a remainder of the via hole after removal of a portion of the via hole.
Public/Granted literature
- US20130112470A1 CIRCUIT BOARDS WITH VIAS EXHIBITING REDUCED VIA CAPACITANCE Public/Granted day:2013-05-09
Information query