Invention Grant
US09034712B2 Stress enhanced LDMOS transistor to minimize on-resistance and maintain high breakdown voltage 有权
应力增强LDMOS晶体管,以最小化导通电阻并保持高击穿电压

Stress enhanced LDMOS transistor to minimize on-resistance and maintain high breakdown voltage
Abstract:
A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate.
Information query
Patent Agency Ranking
0/0