A data write circuit of a semiconductor apparatus includes a data path configured to receive a pattern signal and generate a first delayed pattern signal; a data strobe signal path configured to receive the pattern signal and generate a second delayed pattern signal; a data latch block configured to latch the first delayed pattern signal in response to the second delayed pattern signal, and output a resultant signal; and a control block configured to generate the pattern signal, and vary a delay time of the data path according to a result of comparing phases of a latched signal of the data latch block and the pattern signal.