Invention Grant
- Patent Title: System and method for manufacturing three dimensional integrated circuits
- Patent Title (中): 制造三维集成电路的系统和方法
-
Application No.: US13225404Application Date: 2011-09-02
-
Publication No.: US09025136B2Publication Date: 2015-05-05
- Inventor: Jang Fung Chen , Thomas Laidig
- Applicant: Jang Fung Chen , Thomas Laidig
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Main IPC: G03B27/44
- IPC: G03B27/44 ; G03F7/20

Abstract:
System and method for manufacturing three-dimensional integrated circuits are disclosed. In one embodiment, the method includes providing an imaging writer system that includes a plurality of spatial light modulator (SLM) imaging units arranged in one or more parallel arrays, receiving mask data to be written to one or more layers of the three-dimensional integrated circuit, processing the mask data to form a plurality of partitioned mask data patterns corresponding to the one or more layers of the three-dimensional integrated circuit, assigning one or more SLM imaging units to handle each of the partitioned mask data pattern, and controlling the plurality of SLM imaging units to write the plurality of partitioned mask data patterns to the one or more layers of the three-dimensional integrated circuits in parallel. The method of assigning performs at least one of scaling, alignment, inter-ocular displacement, rotational factor, or substrate deformation correction.
Public/Granted literature
- US20120026478A1 System and Method for Manufacturing Three Dimensional Integrated Circuits Public/Granted day:2012-02-02
Information query