Invention Grant
- Patent Title: Logical Verification Apparatus and Method
- Patent Title (中): 逻辑验证装置及方法
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Application No.: US14244483Application Date: 2014-04-03
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Publication No.: US08990747B2Publication Date: 2015-03-24
- Inventor: Motoya Tanigawa , Noriyuki Ikeda , Akiji Watanabe , Jun Tanowaki
- Applicant: Fujitsu Semiconductor Limited
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Yokohama
- Agency: Staas & Halsey LLP
- Priority: JP2013-079691 20130405
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A verification item extraction apparatus is disclosed that performs a priority determination process. Connection relationships pertinent to input/output are derived for each of logics in a verification subject circuit based on connection information acquired from description data in a storage part. A first priority for verifying the logics is determined based on the connection relationships being derived. Related I/Fs, which are related to inputs to the logics and are interfaces to an outside of the verification subject circuit, are extracted based on the connection information. Second priority for verifying the related I/Fs is determined based on the first priority.
Public/Granted literature
- US20140304669A1 VERIFICATION ITEM EXTRACTION APPARATUS AND METHOD Public/Granted day:2014-10-09
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