An intermediate circuit and method for hiding refresh confliction. The intermediate circuit includes: a first control circuit configured to generate a Command Output Enable signal CON, a Data Read Enable signal DRN and a Refresh Enable signal REFN based on the second clock, wherein a ration of duration the signal CON is in a first state to duration in a second state equals to CLK2/(CLK1-CLK2), the signal REFN has a state that is reverse to that of the signal CON and is used to refresh the DRAM; a command buffer configured to store the access commands received from the user interface and output the stored access commands to the DRAM in response to the first state of the signal CON; a data buffer configured to read data from the DRAM in response to the first state of the signal CON and output the read data.