Invention Grant
- Patent Title: Biasing scheme for large format CMOS active pixel sensors
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Application No.: US12216430Application Date: 2008-07-03
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Publication No.: US08988568B2Publication Date: 2015-03-24
- Inventor: Junichi Nakamura , Isao Takayanagi
- Applicant: Junichi Nakamura , Isao Takayanagi
- Applicant Address: unknown Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: unknown Boise
- Agency: Dickstein Shapiro LLP
- Main IPC: H04N3/14
- IPC: H04N3/14 ; H04N5/365 ; H04N5/357 ; H04N5/3745 ; H04N5/378

Abstract:
An image sensor includes circuitry compensating for voltage drops in a VSS line. The image sensor includes a plurality of photoreceptors arranged in a pixel array having a number of column lines, and read-out circuitry on the column lines. The read-out circuitry provides substantially equal currents on each column line so as to compensate for voltage drops in the VSS line and provide more accurate pixel signals. The image sensor also includes circuitry for filtering noise from a voltage supply line, and for providing hard and/or soft reset operations.
Public/Granted literature
- US20090002536A1 Biasing scheme for large format CMOS active pixel sensors Public/Granted day:2009-01-01
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