Invention Grant
US08972707B2 Multi-core processor with core selectively disabled by kill instruction of system software and resettable only via external pin
有权
多核处理器通过系统软件的kill指令选择性地禁用，只能通过外部引脚复位
- Patent Title: Multi-core processor with core selectively disabled by kill instruction of system software and resettable only via external pin
- Patent Title (中): 多核处理器通过系统软件的kill指令选择性地禁用，只能通过外部引脚复位
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Application No.: US13299239Application Date: 2011-11-17
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Publication No.: US08972707B2Publication Date: 2015-03-03
- Inventor: G. Glenn Henry , Stephan Gaskins
- Applicant: G. Glenn Henry , Stephan Gaskins
- Applicant Address: TW New Taipei
- Assignee: VIA Technologies, Inc.
- Current Assignee: VIA Technologies, Inc.
- Current Assignee Address: TW New Taipei
- Agent E. Alan Davis; James W. Huffman
- Main IPC: G06F1/32
- IPC: G06F1/32 ; G06F1/24 ; G06F9/30 ; G06F9/50 ; G06F11/36 ; G06F11/14
Abstract:
Dynamically reconfigurable multi-core microprocessors and associated methods are provided. A multi-core microprocessor is provided that supports the ability of system software to disable, or kill, selected cores in such a way that they do not cause drag on the processor bus shared with the other cores. Another multi-core microprocessor is provided that supports reconfiguration of an inter-core coordination system of the microprocessor, wherein cores may be selectively designated as masters for purposes of driving signals onto an inter-core communication wire.
Public/Granted literature
- US20120166764A1 DYNAMIC AND SELECTIVE CORE DISABLEMENT AND RECONFIGURATION IN A MULTI-CORE PROCESSOR Public/Granted day:2012-06-28
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