Invention Grant
- Patent Title: Low latency two-level interrupt controller interface to multi-threaded processor
- Patent Title (中): 低延迟两级中断控制器接口到多线程处理器
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Application No.: US13252670Application Date: 2011-10-04
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Publication No.: US08972642B2Publication Date: 2015-03-03
- Inventor: Suresh K. Venkumahanti , Lucian Codrescu , Erich James Plondke , Xufeng Chen , Peixin Zhong
- Applicant: Suresh K. Venkumahanti , Lucian Codrescu , Erich James Plondke , Xufeng Chen , Peixin Zhong
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Peter Michael Kamarchik; Nicholas J. Pauley; Joseph Agusta
- Main IPC: G06F13/24
- IPC: G06F13/24 ; G06F13/32
Abstract:
Systems and method for reducing interrupt latency time in a multi-threaded processor. A first interrupt controller is coupled to the multi-threaded processor. A second interrupt controller is configured to communicate a first interrupt and a first vector identifier to the first interrupt controller, wherein the first interrupt controller is configured to process the first interrupt and the first vector identifier and send the processed interrupt to a thread in the multi-threaded processor. Logic is configured to determine when the multi-threaded processor is ready to receive a second interrupt. A dedicated line is used to communicate an indication to the second interrupt controller that the multi-threaded processor is ready to receive the second interrupt.
Public/Granted literature
- US20130086290A1 Low Latency Two-Level Interrupt Controller Interface to Multi-Threaded Processor Public/Granted day:2013-04-04
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