Invention Grant
- Patent Title: Word line selection circuit and row decoder
- Patent Title (中): 字线选择电路和行解码器
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Application No.: US14319442Application Date: 2014-06-30
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Publication No.: US08971148B2Publication Date: 2015-03-03
- Inventor: Hiroyuki Takahashi , Masahiro Yoshida , Noriaki Takeda
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Foley & Lardner LLP
- Priority: JP2009-127676 20090527; JP2010-027902 20100210
- Main IPC: G11C8/08
- IPC: G11C8/08 ; G11C13/00

Abstract:
A first exemplary aspect of the present invention is a word line selection circuit where address decode signals composed of a power supply voltage and a first voltage lower than a ground voltage are input, and that a word line selection signal composed of the first voltage and a second voltage higher than the power supply voltage is output not via a level shift circuit according to the address decode signals.
Public/Granted literature
- US20140313815A1 WORD LINE SELECTION CIRCUIT AND ROW DECODER Public/Granted day:2014-10-23
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