Invention Grant
- Patent Title: Dual-port SRAM with bit line clamping
- Patent Title (中): 双端口SRAM,带位线钳位
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Application No.: US13901853Application Date: 2013-05-24
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Publication No.: US08971146B2Publication Date: 2015-03-03
- Inventor: Brad Sharpe-Geisler , Timothy Scott Swensen , Sam Tsai , Fabiano Fontana
- Applicant: Lattice Semiconductor Corporation
- Applicant Address: US OR Hillsboro
- Assignee: Lattice Semiconductor Corporation
- Current Assignee: Lattice Semiconductor Corporation
- Current Assignee Address: US OR Hillsboro
- Main IPC: G11C8/00
- IPC: G11C8/00 ; G11C11/419 ; G11C7/12 ; G11C7/18 ; G11C8/16

Abstract:
In one embodiment, a memory includes a plurality of bit lines and a write driver for driving a driven bit line selected from the plurality of bit lines during a write operation. The write driver is coupled to an internal node. A first stage clamping circuit is operable to clamp the internal node to a clamping voltage if the write operation is not enabled and is further operable to unclamp the internal node during the write operation. The memory further includes a multiplexer for selectively coupling the driven bit line to the internal node. A second stage clamping circuit is operable to clamp the plurality of bit lines to a clamping voltage if the write operation is not enabled and is further operable to unclamp the driven bit line during the write operation.
Public/Granted literature
- US20130258761A1 DUAL-PORT SRAM WITH BIT LINE CLAMPING Public/Granted day:2013-10-03
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