Invention Grant
US08971146B2 Dual-port SRAM with bit line clamping 有权
双端口SRAM,带位线钳位

Dual-port SRAM with bit line clamping
Abstract:
In one embodiment, a memory includes a plurality of bit lines and a write driver for driving a driven bit line selected from the plurality of bit lines during a write operation. The write driver is coupled to an internal node. A first stage clamping circuit is operable to clamp the internal node to a clamping voltage if the write operation is not enabled and is further operable to unclamp the internal node during the write operation. The memory further includes a multiplexer for selectively coupling the driven bit line to the internal node. A second stage clamping circuit is operable to clamp the plurality of bit lines to a clamping voltage if the write operation is not enabled and is further operable to unclamp the driven bit line during the write operation.
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