Disclosed is a memory control device, including: an address mapping unit configured to assign a main scanning address and a sub-scanning address to a column address, a row address and a bank address of an SDRAM, to assign lower N bit(s) (N is a positive integer) for indicating an address corresponding to a burst size of a burst transfer among the main scanning address, to lower bit(s) of the column address, and to assign predetermined number of bit(s) arranged successively to an upper bit side of the lower N bit(s) among the main scanning address, to the bank address; and an access executing unit configured to read or write one line of image data in the main scanning direction by carrying out the burst transfer successively multiple times in a multibank operation while the sub-scanning address is changed at an end of the burst transfer.