Invention Grant
- Patent Title: Integrated circuit packaging system with vertical interconnects and method of manufacture thereof
- Patent Title (中): 具有垂直互连的集成电路封装系统及其制造方法
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Application No.: US13167631Application Date: 2011-06-23
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Publication No.: US08970044B2Publication Date: 2015-03-03
- Inventor: A Leam Choi , DongSam Park , YongDuk Lee
- Applicant: A Leam Choi , DongSam Park , YongDuk Lee
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Ltd.
- Current Assignee: STATS ChipPAC Ltd.
- Current Assignee Address: SG Singapore
- Agency: Ishimaru & Associates LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/56 ; H01L23/498 ; H01L25/10 ; H01L25/03 ; H01L25/00 ; H01L21/48 ; H01L23/31 ; H01L23/00

Abstract:
A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate; forming an encapsulation over the integrated circuit, the encapsulation having an encapsulation interior sidewall; forming a peripheral non-horizontal conductive plate directly on the encapsulation interior sidewall; and forming a peripheral vertical conductor directly on the peripheral non-horizontal conductive plate and the substrate.
Public/Granted literature
- US20120326325A1 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF Public/Granted day:2012-12-27
Information query
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