Invention Grant
- Patent Title: Stress relieving second level interconnect structures and methods of making the same
- Patent Title (中): 应力消除二级互连结构及其制作方法
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Application No.: US13825815Application Date: 2011-09-20
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Publication No.: US08970036B2Publication Date: 2015-03-03
- Inventor: Pulugurtha Markondeya Raj , Nitesh Kumbhat , Venkatesh V. Sundaram , Rao R. Tummala , Xian Qin
- Applicant: Pulugurtha Markondeya Raj , Nitesh Kumbhat , Venkatesh V. Sundaram , Rao R. Tummala , Xian Qin
- Applicant Address: US GA Atlanta
- Assignee: Georgia Tech Research Corporation
- Current Assignee: Georgia Tech Research Corporation
- Current Assignee Address: US GA Atlanta
- Agency: Troutman Sanders LLP
- Agent Ryan A. Schneider; Elizabeth-Ann Weeks
- International Application: PCT/US2011/052384 WO 20110920
- International Announcement: WO2012/047506 WO 20120412
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/00 ; H05K3/34 ; H05K3/40 ; H05K1/02

Abstract:
Provided is a stress-relieving, second-level interconnect structure that is low-cost and accommodates thermal coefficient of expansion (TCE) mismatch between low-TCE packages and printed circuit boards (PCBs). The interconnect structure comprises at least a first pad, a supporting pillar, and a solder bump, wherein the first pad and supporting pillar are operative to absorb substantially all plastic strain, thereby enhancing compliance between the two electronic components.
Public/Granted literature
- US20130270695A1 Second Level Interconnect Structures and Methods of Making the Same Public/Granted day:2013-10-17
Information query
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