Invention Grant
- Patent Title: Methods and structures for reducing stress on die assembly
- Patent Title (中): 降低模具组装应力的方法和结构
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Application No.: US13764958Application Date: 2013-02-12
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Publication No.: US08970026B2Publication Date: 2015-03-03
- Inventor: George R. Leal , Leo M. Higgins, III , Tim V. Pham
- Applicant: George R. Leal , Leo M. Higgins, III , Tim V. Pham
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Mary Jo Bertani
- Main IPC: B23K35/24
- IPC: B23K35/24 ; H01L23/498 ; H01L23/00
Abstract:
A first set of electrically conductive cladding is disposed on an inner section of one external side of a package substrate. The first set electrically conductive cladding is fabricated with a first solder compound. A second set of electrically conductive cladding is disposed on an outer section of the one external side of the substrate. The second set of electrically conductive cladding consists of a second solder compound. The outer section can be farther away from a center of the one external side of the substrate than the inner section. During a reflow process, the first and second solder compounds are configured to become completely molten when heated and the first solder compound solidifies at a higher temperature during cool down than the second solder compound.
Public/Granted literature
- US20140225268A1 METHODS AND STRUCTURES FOR REDUCING STRESS ON DIE ASSEMBLY Public/Granted day:2014-08-14
Information query
IPC分类:
