Invention Grant
US08969952B2 Semiconductor device with reduced miller capacitance and fabrication method thereof
有权
具有降低的铣削电容的半导体器件及其制造方法
- Patent Title: Semiconductor device with reduced miller capacitance and fabrication method thereof
- Patent Title (中): 具有降低的铣削电容的半导体器件及其制造方法
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Application No.: US13742320Application Date: 2013-01-15
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Publication No.: US08969952B2Publication Date: 2015-03-03
- Inventor: Yung-Fa Lin
- Applicant: Anpec Electronics Corporation
- Applicant Address: TW Hsinchu Science Park, Hsin-Chu
- Assignee: Anpec Electronics Corporation
- Current Assignee: Anpec Electronics Corporation
- Current Assignee Address: TW Hsinchu Science Park, Hsin-Chu
- Agent Winston Hsu; Scott Margo
- Priority: TW101143944A 20121123
- Main IPC: H01L29/78
- IPC: H01L29/78

Abstract:
A semiconductor power device includes an epitaxial layer grown on a semiconductor substrate; an ion well with a junction depth in the epitaxial layer; a gate trench with a depth deeper than the junction depth in the ion well; a gate oxide layer in the gate trench; a gate embedded the gate trench; and a pocket doping region in the epitaxial layer. The pocket doping region is adjacent to and covers at least a corner of the gate trench.
Public/Granted literature
- US20140145258A1 SEMICONDUCTOR DEVICE WITH REDUCED MILLER CAPACITANCE AND FABRICATION METHOD THEREOF Public/Granted day:2014-05-29
Information query
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