Invention Grant
- Patent Title: Methods for fabricating semiconductor device structures and arrays of vertical transistor devices
- Patent Title (中): 制造半导体器件结构和垂直晶体管器件阵列的方法
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Application No.: US13215968Application Date: 2011-08-23
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Publication No.: US08969154B2Publication Date: 2015-03-03
- Inventor: Gurtej S. Sandhu
- Applicant: Gurtej S. Sandhu
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: H01L29/772
- IPC: H01L29/772 ; B82Y10/00 ; H01L29/66 ; H01L27/105 ; H01L21/8234 ; H01L29/78
Abstract:
A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate. The mesa has a channel region between a first side and second side of the mesa. A first gate is on a first side of the mesa, the first gate comprising a first gate insulator and a first gate conductor comprising graphene overlying the first gate insulator. The gate conductor may comprise graphene in one or more monolayers. Also disclosed are a method for fabricating the semiconductor device structure; an array of vertical transistor devices, including semiconductor devices having the structure disclosed; and a method for fabricating the array of vertical transistor devices.
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