Invention Grant
- Patent Title: Memory controller
- Patent Title (中): 内存控制器
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Application No.: US13423566Application Date: 2012-03-19
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Publication No.: US08949690B2Publication Date: 2015-02-03
- Inventor: Takahiko Sugahara , Eri Fukushita
- Applicant: Takahiko Sugahara , Eri Fukushita
- Applicant Address: JP Osaka-shi
- Assignee: MegaChips Corporation
- Current Assignee: MegaChips Corporation
- Current Assignee Address: JP Osaka-shi
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2011-131246 20110613
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G06F11/10 ; H03M13/05 ; H03M13/37

Abstract:
An ECC circuit can operate in a plurality of error correction modes with different correcting capabilities for data stored in a memory. The ECC circuit calculates a syndrome with respect to information data in accordance with an error correction mode set by a control part and adds a syndrome of a fixed length in which dummy bits are added to the calculated syndrome, to the information data. When code data is read out, the ECC circuit performs a correction process on the code data by using the syndrome included in the code data.
Public/Granted literature
- US20120317463A1 MEMORY CONTROLLER Public/Granted day:2012-12-13
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