A semiconductor memory device includes at least one memory cell connected to an internal voltage line that receives a cell power supply voltage and a write assist circuit connected to the internal voltage line. The write assist circuit lowers a level of the cell power supply voltage to a target level during a first period of a write operation on the memory cell and maintains the level of the cell power supply voltage at the target level during a second period of the write operation based on a write assist control signal. The second period succeeds the first period.