Invention Grant
- Patent Title: Memory error management system
- Patent Title (中): 内存错误管理系统
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Application No.: US13759054Application Date: 2013-02-05
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Publication No.: US08843791B2Publication Date: 2014-09-23
- Inventor: Sarthak Mittal , Kshitij Bajaj , Prashant Bhargava
- Applicant: Sarthak Mittal , Kshitij Bajaj , Prashant Bhargava
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Charles Bergere
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/07

Abstract:
A memory error management system connected to memory channels for managing errors detected in corresponding memory devices includes a reporting table including a list of historically reported errors, a binary value representing the current error status of the memory channels, a uniqueness check module for checking whether a historically reported error is reappearing as a current error, an error mask register for generating a masked binary value representing unique current errors in the memory channels, and a channel arbitration module for decoding the channel identifiers of corrupted memory channels from the masked binary value and storing the decoded channel identifiers into the reporting table.
Public/Granted literature
- US20140223239A1 MEMORY ERROR MANAGEMENT SYSTEM Public/Granted day:2014-08-07
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